The narrow processing of memory is making progress as semiconductor manufacturing technology advances. As a result, the time during which a memory retains data is getting shorter, and power consumption is increasing due to frequent refresh operations. The decline in data-retaining time due to deterioration in memory's current-carrying performance is also one of the causes of malfunction.
On the other hand, demand for much lower power consumption is increasing as the use of portable information devices such as notebook computer has become more widespread.
A current typical refresh operation is to periodically refresh a memory. For example, it is usual for a 512-Mbit SDRAM to perform the refresh operation of 32,768 Row lines within 64 ms. One refresh command allows four Row addresses to be refreshed. Therefore, the refresh commands are transmitted at intervals of 7.8 μs (nearly equal to the result of the following calculation: 64 ms/(32768/4)).
Conventional techniques are disclosed in the following documents:    [Patent Document 1] Japanese Laid-open Patent Publication No. 2002-319282    [Patent Document 2] Japanese Laid-open Patent Publication No. 2002-230970    [Patent Document 3] Japanese Laid-open Patent Publication No. 7-176185